Our FPGA-based prototyping platform is designed for large-scale ASIC/SoC hardware-software co-verification across diverse applications, including intelligent driving, data centers, artificial intelligence, 5G communications, and smartphone SoCs. It delivers an efficient verification solution that significantly reduces development cycles and accelerates time-to-market.
Key Features:
Currently deployed in commercial systems scaling up to 160 interconnected VU19P FPGAs, achieving over 600 million logic gates
Global Timing-Driven Auto-Partitioning Engine maintains high-performance operation at 10MHz even in ultra-large-scale systems
Scalable interconnect architecture supports flexible system expansion
Prototyping mode: 20+ MHz
Emulation mode: 10 MHz
Equipped with an advanced timing analysis engine, the Intelligent Compilation Software,a core proprietary technology—maximizes FPGA-based verification system performance.
Deployed in commercial applications, our massively scalable systems support single designs exceeding 600 million gates with proven stability.
Integrated Compiler & Runtime Software speeds up debugging and optimizes design input, constraints, and workflow.
40%–60% faster design bring-up vs. traditional solutions, accelerating RTL-to-running-system iterations.
Full-signal visibility during runtime—generate waveforms without recompilation, drastically reducing debug cycles.
UPF-based low-power design verification
SystemC/DPI-C testbench integration
Hybrid virtual-platform co-simulation enables shift-left SW development & HW/SW architecture exploration.
Supports a wide range of high-speed I/O adapters, virtual interface models, and memory models, including:
PCIe Gen5, Ethernet, MIPI
DDR5, HBM3, and more